1. Field of Invention
The present invention relates to a MOS process sequence. More particularly, the present invention relates to a salicide process.
2. Description of Related Art
FIGS. 1A-1C are schematic, cross-sectional views of a conventional salicide process.
As shown in Fig. 1A, several device isolation regions 102 are formed and over a substrate 100. A thin oxide layer 104 is formed between the isolation regions 102 over the substrate 100. A gate 106 and a gate sidewall spacer 108 thereof are formed over the thin oxide layer 104.
As shown in FIG. 1B, ions are implanted into the substrate 100. An annealing step is then performed to form source/drain regions 110.
As shown in FIG. 1C, the gate 106 and the source/drain regions 110 are covered by a silicide film 112. Because those silicide films 112 are formed using a self-aligned process that does not entail any additional masking steps, the silicide-covering process is referred to as a salicide process.
The salicide process in a CMOS process reduces the gate resistance. However, the gate resistance, such as gate sheet resistance, increases as the gate length reduces. On the other hand, increasing the gate area is important to improve the gate sheet resistance. Therefore, there is a need for a new salicide process that can increase the gate area to improve the gate resistance.